On Predictable Reconfigurable System Design

We propose a design methodology to facilitate rigorous development of complex applications targeting reconfigurable hardware. Our relies on analytical estimation system performance and area utilisation for given specific application particular instance consisting controlflow machine working in conjunction with one or more dataflow accelerators. The targeted is carefully analyzed, the parts identified hardware acceleration are reimplemented as set representative software models. Next, results analysis, suitable architecture devised its evaluated determine bottlenecks, allowing predictable design. iteratively refined, until final version satisfying specification requirements terms required obtained. validate presented using widely accepted convolutional neural network (VGG-16) an important HPC (BQCD). In both cases, our relieved alleviated all bottlenecks before implementation was started. As result architectures were implemented first time right, achieving state-of-the-art within 15% modelling estimations.